This invention relates to weak current generation.
Weak current generation plays a part, for example, in a weak write test mode (WWTM) for static random access memories (SRAMs). The WWTM uses test circuitry that attempts to overwrite data stored in cells of an SRAM. Cells in which the data is successfully overwritten are considered to be defective. (See Weak Write Test mode: A SRAM Cell Stability Design for Test Technique, IEEE Intentional Test Conference, July 1997, incorporated by reference).
As shown in FIG. 1, an SRAM column, for example, can be driven by an SRAM column write driver 10. Driver 10 uses conventional inverters 16, 18 (comprised of devices 20, 22, 26, 28) to invert, respectively, input signal din 24 to produce bit #12 and input signal din #30 to produce bit 14.
In normal operation, a weak write control signal weak #32 is held high (logic 1), keeping p-device 34 on and (through inverter 38) p-device 36 off. n-device 40 is also kept on.
Driver 10 is placed into WWTM mode by driving weak #32 low, which switches device 34 on and device 36 off. Device 40 also turns off. Diode-connected transistor 44 then supplies a weak write current onto either bit 12 or bit #14, depending on which of the inputs din or din # is on. By a xe2x80x9cweakxe2x80x9d current we mean a current in the range of tens of nano-amperes to a few micro amperes.
The diode-connected transistor 44 is carefully sized using SPICE simulations, but mismatches can occur between the simulation and the related physical device (e.g., a fabricated chip).
Multiple diodes can be stacked to obtain different current values.